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5T9306 - Block Diagram
5T9306 - Pinout


2.5V LVDS,1:6 Clock Buffer Terabuffer™ II

The 5T9306 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9306 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 5T9306 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.


  • Guaranteed Low Skew < 25ps (max)
  • Very low duty cycle distortion < 125ps (max)
  • High speed propagation delay < 1.75ns (max)
  • Additive phase jitter, RMS 0.159ps (typical) @ 125MHz
  • Up to 1GHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V / 2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input interface
  • Selectable differential inputs to six LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • Available in VFQFPN package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
6LVDS0.000000 - 1000.0000000.000000 - 1000.0000002LVDS, HSTL, LVPECL, CML, LVCMOS1, 62.5250.159

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5T9306NLGIActiveNLG28VFQFPN28IYesTrayCheck Availability
5T9306NLGI8ActiveNLG28VFQFPN28IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
IDT5T9306 Data Sheet Datasheet PDF 159 KB Nov 7, 2013
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 14, 2012
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products Product Change Notice PDF 80 KB Dec 14, 2004
PCN#: L-0405-04 To comply with current EIA Std Product Change Notice PDF 143 KB May 18, 2004
show all (4)
PCN#: A-0310-01, Green Products Product Change Notice PDF 26 KB Oct 10, 2003
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
show all (4)
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

Software & Tools

Title Type Format File Size Datesort icon
5T9306 IBIS Model Model - IBIS ZIP 6 KB Apr 22, 2005