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851S201I - Block Diagram
851S201I - Pinout


2:1 Differential-to-HCSL Multiplexer W/Low Input Level Alarm

The 851S201I is a high performance 2:1 Differential-to-HCSL Multiplexer with a 2 output fanout buffer. The 851S201I operates up to 250MHz and accepts HCSL and other low level differential inputs levels. Input level detection circuitry is available to flag input levels that drops below a specified value and on the selected input. This signal is latched until the status is reset via the alarm reset input. The 851S201I is packaged in a small 3mm x 3mm 16 lead VFQFN package, making it ideal for use on space constrained boards.


  • Two differential HCSL output pairs
  • Two selectable differential clock input pairs
  • CLKx, nCLKx pairs can accept HCSL level inputs
  • Low level input detection on selected input (latched)
  • Maximum Input frequency : 250MHz
  • Output skew: 5ps (typical)
  • Propagation delay: 1.4ns (typical)
  • Additive RMS phase jitter at 133.33MHz (12kHz - 20MHz): 0.151ps (typical)
  • Full 3.3V operating supply
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) packages

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
2HCSL0.000000 - 250.0000000.000000 - 250.0000002HCSL13.3340.151

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
851S201CKILFActiveNLG16VFQFPN16IYesTubeCheck Availability
851S201CKILFTActiveNLG16VFQFPN16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
851S201I Datasheet Datasheet PDF 423 KB Sep 6, 2013
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016