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85304I-01 - Block Diagram
85304I-01 - Pinout

85304I-01

Low Skew,1-to-5Differential-to-3.3V LVPECL Fanout Buffer

The ICS85304I-01 is a low skew, high performance 1-to-5 Differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the ICS85304I-01 ideal for those applications demanding well defined performance and repeatability.

Features

  • Five 3.3V differential LVPECL output pairs
  • Selectable differential CLKx, nCLKx input pairs
  • CLKx, nCLKx input pairs can accept the following differential levels: LVDS, LVPECL, LVHSTL and HCSL levels
  • Maximum output frequency: 650MHz
  • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx inputs 
  • Output skew: 60ps (maximum) 
  • Part-to-part skew: 300ps (maximum)
  • Propagation delay: 2.1ns (maximum)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
5LVPECL0.000000 - 650.0000000.000000 - 650.0000002HSTL, LVDS, LVPECL, SSTL, HCSL13.335

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
85304AGI-01LFActivePGG20TSSOP20IYesTubeCheck Availability
85304AGI-01LFTActivePGG20TSSOP20IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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ICS85304I-01 Datasheet Datasheet PDF 180 KB Feb 28, 2013
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Apr 14, 2016
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PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB Feb 15, 2016
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
show all (7)
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
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PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 95 KB Oct 22, 2015
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PCN# : A1509-03 Gold to Copper wire Product Change Notice PDF 31 KB Oct 15, 2015
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PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages Product Change Notice PDF 50 KB Jul 21, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016