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854S036 - Block Diagram
854S036 - Pinout


Low Skew,Dual,Differential-to-LVDS Fanout Buffer

The 854S036 is a low skew, high performance Dual Differential-to-LVDS Fanout Buffer. One of the two fanout buffers has 3 LVDS outputs, the other has 6 LVDS outputs. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The 854S036 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S036 ideal for those clock distribution applications demanding well defined performance and repeatability.


  • Two independent differential LVDS output buffers, buffer A with three outputs, buffer B with 6 outputs
  • Two differential clock input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CMLSSTL
  • Output frequency: 2GHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
  • Output skew: 100ps (maximum)
  • Bank skew: 20ps (maximum)
  • Propagation delay: 550ps (maximum)
  • Additive phase jitter, RMS: 0.06ps (typical)
  • Full 3.3V power supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
9LVDS0.000000 - 2000.0000000.000000 - 2000.0000002LVDS, LVPECL, SSTL, CML23.33.31000.06

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
854S036AKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability
854S036AKLFTActiveNLG32P3VFQFPN32CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS854S036 Datasheet Datasheet PDF 762 KB Nov 16, 2009
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
show all (4)
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

Software & Tools

Title Type Format File Size Datesort icon
854S036 IBIS Model Model - IBIS ZIP 31 KB Feb 1, 2011