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854S54I-02 - Block Diagram
854S54I-02 - Pinout


Dual 2:1,1:2 Differential-to-LVDS Multiplexer

The 854S54I-02 is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device is useful for allowing direct Advanced Mezzanine Card (AMC) to Advanced Mezzanine Card communication connected to an Advanced TCA Backplane via Fabric Hub Board. The 854S54I-02 is optimized for applications requiring very high performance and has a maximum operating frequency of 1.75GHz. The device is packaged in a small, 4mm x 4mm VFQFN package, making it ideal for use on space-constrained boards.


  • Three differential LVDS output pairs
  • Three differential data inputs
  • Data pairs can accept the following differential input levels: LVPECL, LVDSSSTL
  • Maximum output frequency: 1.75GHz
  • Propagation delay: 700ps (maximum)
  • Part-to-part skew: 275ps (maximum)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
3LVDS0.000000 - 1750.0000000.000000 - 1750.0000003LVPECL, SSTL, LVDS33.30.073

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
854S54AKI-02LFActiveNLG24P1VFQFPN24IYesTrayCheck Availability
854S54AKI-02LFTActiveNLG24P1VFQFPN24IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS854S54I-02 Datasheet Datasheet PDF 777 KB Jul 30, 2010
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
ICS854S54I-02 IBIS Model Model - IBIS ZIP 38 KB Aug 20, 2010