Skip to main content
879S216I-02 - Block Diagram
879S216I-02 - Pinout

879S216I-02

2:2,Differential-to-LVPECL/LVDS Divider

The 879S216I-02 is a Differential-to-LVPECL/ LVDS Clock Divider which can operate up to 2.5GHz. 879S216I-02 has 2 selectable differential clock inputs. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. 879S216I-02 can divide the input clock by ÷2, ÷4, ÷8 and ÷16. Table 4A lists all the available output dividers.

Features

  • High speed 2:2 differential divider
  • Two differential LVPECL or LVDS output pairs
  • Four selectable divide combinations
  • PCLKx can accept the following input levels: LVPECL, LVDSCML
  • Maximum input frequency: 2.5GHz
  • Propagation delay: 0.8ns (minimum), 1.6ns (maximum)
  • Output Skew: 25ps (maximum)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 5) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
2LVDS, LVPECL0.000000 - 625.000000, 0.000000 - 312.500000, 0.000000 - 156.250000, 0.000000 - 1250.0000000.000000 - 2500.0000002LVDS, LVPECL, CML12.5, 3.32.5, 3.32, 4, 8, 1625

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
879S216AKI-02LFActiveNLG24P1VFQFPN24IYesTubeCheck Availability
879S216AKI-02LFTActiveNLG24P1VFQFPN24IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
879S216I-02 Data Sheet Datasheet PDF 863 KB May 1, 2013
Apps Notes & White Papers
no-lock
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
no-lock
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
no-lock
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
no-lock
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
no-lock
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
no-lock
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
no-lock
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
no-lock
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
no-lock
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
no-lock
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
no-lock
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
no-lock
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
no-lock
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
Other
no-lock
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
no-lock
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016