Skip to main content
8EN31AK 32VFQFN - Block Diagram


1-to-9 Differential-to-3.3V Fanout Buffer

Alternative Products
NOTICE - The following device(s) are recommended alternatives:

The 8EN31AK is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8EN31AK has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteristics make the 8EN31AK ideal for high performance workstation and server applications.


  • Nine differential 3.3V LVPECL outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTLHCSL
  • PCLK, nPCLK supports the following input types: LVPECL, CMLSSTL
  • Maximum output frequency: 500MHz
  • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
  • Output skew: 40ps (maximum)
  • Part-to-part skew: 350ps (maximum)
  • Propagation delay: 1.9ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Available in lead-free RoHS compliant package
  • Industrial temperature information available upon request

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8EN31AKLFLast Time BuyNLG32P3VFQFPN32CYesTrayCheck Availability
8EN31AKLFTLast Time BuyNLG32P3VFQFPN32CYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
8EN31AK Final Data Sheet Datasheet PDF 233 KB Jun 29, 2016
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (11)
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PDN# : CQ-16-01 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 552 KB May 4, 2016
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016