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8R9306I

2.5V LVDS, 1:6 Clock Buffer Terabuffer™II

The 8R9306I 2.5V differential clock buffer is a user-selectable differential input to six LVDS outputs. The fanout from a differential input to six LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 8R9306I can act as a translator from a differential HSTL, eHSTL, LVPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V, 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secondary clock source. Selectable reference inputs are controlled by SEL. The 8R9306I outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

Features

  • Guaranteed low skew: 40ps (maximum) 
  • Very low duty cycle distortion: <125ps (maximum)
  • High speed propagation delay: <1.75ns (maximum)
  • Up to 1GHz operation
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL eHSTL, LVPECL (2.5V), LVPECL (3.3V), CML or LVDS input interface
  • Selectable differential inputs to six LVDS outputs
  • Power-down mode
  • 2.5V VDD
  • -40°C to 85°C ambient operating temperature
  • Available in VFQFPN package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)
6LVDS0.000000 - 1000.0000000.000000 - 1000.0000002HSTL, LVDS, LVCMOS, LVPECL, CML12.540

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8R9306NLGIActiveNLG28VFQFPN28IYesTrayCheck Availability
8R9306NLGI8ActiveNLG28VFQFPN28IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8R9306I Data Sheet Datasheet PDF 644 KB Sep 17, 2013
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : TB1311-01 New Carrier Tape on VFQFPN-28, VFQFPN-40, VFQFPN-48 Product Change Notice PDF 790 KB Apr 8, 2014
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016