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8S89833I - Block Diagram
8S89833I - Pinout


Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer W/Internal Termination

The 8S89833I is a high speed 1-to-4 Differential-to-LVDS Fanout Buffer with Internal Termination. The 8S89833I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The 8S89833I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.


  • Four differential LVDS outputs
  • IN, nIN input pair can accept the following differential input levels: LVPECL, LVDSCML
  • Output frequency: 2GHz
  • Cycle-to-cycle jitter, RMS: 3.5ps (maximum)
  • Additive phase jitter, RMS: 0.03ps (typical)
  • Output skew: 30ps (maximum)
  • Part-to-part skew: 200ps (maximum)
  • Propagation Delay: 600ps (maximum)
  • Full 3.3V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)Divider ValueOutput Skew (ps)Additive Phase Jitter Typ RMS (ps)
4LVDS0.000000 - 2000.0000000.000000 - 2000.0000001LVDS, LVPECL, CML13.33.3300.03

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8S89833AKILFActiveNLG16VFQFPN16IYesTubeCheck Availability
8S89833AKILFTActiveNLG16VFQFPN16IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
8S89833 Datasheet Datasheet PDF 316 KB Aug 24, 2016
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
show all (12)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Software & Tools

Title Type Format File Size Datesort icon
ICS8S89833I IBIS Model Model - IBIS ZIP 37 KB Aug 19, 2010