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VersaClock® 3S Programmable Clock Generator

The 5P35021 is a VersaClock programmable clock generator and is designed for low power, consumer, and high performance PCI Express applications. The 5P35021 device is a three PLL architecture design, and each PLL is individually programmable and allowing for up to five unique
frequency outputs. The 5P35021 has built-in unique features such as Proactive Power Saving (PPS), Performance-Power Balancing (PPB), Overshot Reduction Technology (ORT) and Extreme Low Power DCO. An internal OTP memory allows the user to store the configuration in the device without programming after power up, then program the 5P35021 again through the I2C interface.
The device has programmable VCO and PLL source selection to allow the user to do power-performance optimization based on the application requirements. It also supports one single-ended output and two pair of differential outputs that support LVCMOS, LVPECL, LVDS and LPHCSL. A Low
Power 32.768kHz clock is supported with only less than 5μA current consumption for system RTC reference clock.


  • Configurable OE pin function as OE, PD#, PPS or DFC control function
  • Configurable PLL bandwidth/minimizes jitter peaking
  • PPS: Proactive Power Saving features save power during the end device power down mode
  • PPB: Performance- Power Balancing feature allows minimum power consumption base on required performance
  • DFC: Dynamic Frequency Control feature allows up to 4 difference frequencies switch dynamically
  • Spread Spectrum clock support to lower system EMI
  • I2C interface
  • Also supports crystal input such as the IDT 603-25-150 (25 MHz)

Product Options

This device is customizable. Choose from the options below, or use the Custom Part Configuration Utility now.
Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5P35021-000NDGIActiveNDG20P2VFQFPN20IYesTrayCheck Availability
5P35021-000NDGI8ActiveNDG20P2VFQFPN20IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
5P35021 Datasheet Datasheet PDF 387 KB Sep 20, 2016
User Guides & Manuals
Timing Commander Software for VersaClock 3S - 5P3502x Manual - Software PDF 1.55 MB Aug 22, 2016
VersaClock 3S - 5P3502x Family Programmer Board User Guide Manual PDF 1.18 MB May 27, 2016
Timing Commander Installation Guide Guide PDF 497 KB Oct 7, 2013
Apps Notes & White Papers
AN-909 PCB Layout Considerations for Designing IDT VersaClock 3S, 5 and 6 Clock Products Application Note PDF 743 KB Jul 1, 2016
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB Mar 10, 2016
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
show all (10)
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB Jan 15, 2014
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
5P35021 Reference Schematic Schematic PDF 20 KB Jun 9, 2016
VersaClock 3S Programmable Clocks Product Brief 简体中文, 日本語 Product Brief PDF 234 KB May 27, 2016
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs Technical Brief PDF 238 KB Feb 8, 2016
show all (4)
VersaClock Family of Programmable Clocks Overview 日本語 Overview PDF 598 KB Jan 18, 2016

Software & Tools

Title Type Format File Size Datesort icon
5P35021 IBIS Model Model - IBIS ZIP 74 KB May 17, 2016
Timing Commander Installer v1.7.3.3 Software ZIP 17.87 MB May 12, 2016
VersaClock 3S Timing Commander Personality File Software TCP 4.62 MB Aug 17, 2016

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