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181-53 - Block Diagram
181-53 - Pinout


Low EMI Clock Generator

The 181-53 generates a low EMI output clock from a clock or crystal input. The device uses IDT’s proprietary mix of analog and digital Phase Locked Loop (PLL) technology to spread the frequency spectrum of the output, thereby reducing the frequency amplitude peaks by several dB. The 181-53 offers center spread selection of +/-0.625% and +/-1.875%. Refer to the MK1714-01/02 for the widest selection of input frequencies and multipliers. IDT offers a complete line of EMI reducing clock generators. Consult us when you need to remove crystals and oscillators from your board.


  • Pin and function compatible to Cypress W181-53
  • Packaged in 8-pin SOIC
  • Provides a spread spectrum output clock
  • Accepts a clock input and provides same frequency dithered output
  • Input frequency of 46 to 75 MHz for Clock input
  • Peak reduction by 7dB - 14dB typical on 3rd - 19th odd harmonics
  • Spread percentage selection for +/-0.625% and +/-1.875%
  • Operating voltage of 3.3 V and 5 V
  • Advanced, low-power CMOS process

Product Specification

Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
LVCMOS46.000000 - 75.00000046.000000 - 75.0000001LVCMOS13.3, 53.3, 5

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
181M-53LFObsoleteDCG8SOIC8CYesTubeCheck Availability
181M-53LFTObsoleteDCG8SOIC8CYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
181-53 Datasheet Datasheet PDF 143 KB May 14, 2010
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB Oct 6, 2006