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5T2010 - Block Diagram


2.5V Zero Delay PLL Clock Driver Teraclock

Alternative Products
NOTICE - The following device(s) are recommended alternatives:
Functionally compatible
Functionally compatible

The 5T2010 is a 2.5V PLL clock driver intended for high performance computing and data-communications applications. The 5T2010 has ten outputs in five banks of two, plus a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent. The feedback bank allows divide-by-functionality from 1 to 12 through the use of the DS[1:0] inputs. This provides the user with frequency multiplication 1 to 12 without using divided outputs for feedback. Each output bank also allows for a divide-by functionality of 2 or 4. The 5T2010 features a user-selectable, single-ended or differential input to ten single-ended outputs. The clock driver also acts as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. The outputs can be synchronously enabled/disabled. Furthermore, when PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When PE is held low, all the outputs are synchronized with the negative edge of REF.


  • 2.5 VDD
  • 5 pairs of outputs
  • Low skew: 50ps same pair, 100ps all outputs
  • Selectable positive or negative edge synchronization
  • Tolerant of spread spectrum input clock
  • Synchronous output enable
  • Selectable inputs
  • Input frequency: 4.17MHz to 250MHz
  • Output frequency: 12.5MHz to 250MHz
  • 1.8V / 2.5V LVTTL: up to 250MHz
  • HSTL / eHSTL: up to 250MHz
  • Hot insertable and over-voltage tolerant inputs
  • 3-level inputs for selectable interface
  • 3-level inputs for feedback divide selection with multiply ratios of(1-6, 8, 10, 12)
  • Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
  • interface
  • Selectable differential or single-ended inputs and ten singleended
  • outputs
  • PLL bypass for DC testing
  • External differential feedback, internal loop filter
  • Low Jitter: <75ps cycle-to-cycle
  • Power-down mode
  • Lock indicator

Product Specification

Core Voltage (V)Input Freq (MHz)Inputs (#)Input TypeOutput Voltage (V)Output Freq Range (MHz)Output TypeOutputs (#)C-C Jitter Max P-P (ps)
2.54.170000 - 250.0000002LVTTL, LVCMOS, LVPECL, HSTL2.512.500000 - 250.000000LVCMOS, HSTL575

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
5T2010NLGIObsoleteNLG68VFQFPN68IYesTrayCheck Availability
5T2010NLGI8ObsoleteNLG68VFQFPN68IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Apps Notes & White Papers
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
show all (14)
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
AN-237: PLL Lock Indicator Application Note PDF 200 KB Jul 6, 2005
AN-237: PLL Lock Indicator Application Note PDF 200 KB Jul 6, 2005
PDN# : CQ-13-02 (R1) PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 601 KB Dec 22, 2013
PDN# : CQ-13-02 Q2FY14 Quarter PDN for Manufacturing Discontinuance Product Discontinuation Notice PDF 327 KB Oct 27, 2013
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w Product Change Notice PDF 24 KB Nov 14, 2012
show all (10)
PCN# A-0605-07 Transfer 144, 240, 260, 324L PBGA from ATK to ATP Product Change Notice PDF 99 KB Jun 14, 2006
PCN#: TB-0512-01 Reel Color Changed from Blue to Black Product Change Notice PDF 729 KB Dec 16, 2005
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products Product Change Notice PDF 80 KB Dec 14, 2004
PCN#: A-0403-03, BGA package family Product Change Notice PDF 38 KB Dec 9, 2004
PCN#: L-0405-04 To comply with current EIA Std Product Change Notice PDF 143 KB May 18, 2004
PCN#: A-0309-05, new m/c-G770 & d/a-2300 material Product Change Notice PDF 211 KB Oct 16, 2003
PCN#: A-0310-01, Green Products Product Change Notice PDF 26 KB Oct 10, 2003
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016