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DDR3 Register + PLL

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V, 1.35V and 1.5V VDD operation


  • DDR3-800/1066/1333/1600/1866/2133 rate
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
  • Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
  • Supports LVCMOS switching levels on the RESET and MIRROR inputs
  • Checks priority on DIMM-independent data inputs
  • Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
  • Supports CKE Power Down operation modes
  • Supports Quad Chip Select operation features
  • RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
  • Provides access to internal control words for configuring the device features and adapting in different RDIMM and   system applications
  • Latch-up performance exceeds 100mA
  • ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)

Product Specification

SDRAM TypeFunctionPkg. CodePkg. TypeLength (mm)Width (mm)Temp. Grade
DDR3-800 to 2133Register + PLLAKG176CABGA13.58C

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
SSTE32882KA1AKGActiveAKG176CABGA176CYesTrayCheck Availability
SSTE32882KA1AKG8ActiveAKG176CABGA176CYesReelCheck Availability