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71124 - Block Diagram


5.0V 128K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout

The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.


  • JEDEC revolutionary pinout (center power/GND) for reduced noise.
  • Equal access and cycle times – Commercial and Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional inputs and outputs directly TTL-compatible
  • Low power consumption via chip deselect
  • Available in a 32-pin 400 mil Plastic SOJ packages

Product Specification

Density (Kb)Bus Width (bits)Core Voltage (V)Pkg. CodeOrganizationI/O Voltage (V)Access Time (ns)I/O Frequency (MHz)Temp. RangeArchitectureOutput Type
102485PBG32128K x 85.0012, 15, 20-40 to 85°C, 0 to 70°CAsynchronous

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
71124S12YGActivePBG32SOJ32CYesTubeCheck Availability
71124S12YG8ActivePBG32SOJ32CYesReelCheck Availability
71124S15YGActivePBG32SOJ32CYesTubeCheck Availability
71124S15YG8ActivePBG32SOJ32CYesReelCheck Availability
71124S15YGIActivePBG32SOJ32IYesTubeCheck Availability
71124S15YGI8ActivePBG32SOJ32IYesReelCheck Availability
71124S20YGActivePBG32SOJ32CYesTubeCheck Availability
71124S20YG8ActivePBG32SOJ32CYesReelCheck Availability
71124S20YGIActivePBG32SOJ32IYesTubeCheck Availability
71124S20YGI8ActivePBG32SOJ32IYesReelCheck Availability


Technical Documentation

Title Type Format File Size Datesort icon
Datasheets & Errata
71124 Data Sheet Datasheet PDF 78 KB Nov 3, 2014

Software & Tools

Title Type Format File Size Datesort icon
71124 IBIS Model Model - IBIS ZIP 5 KB Dec 22, 1999