5.0V 128K x 8 Asynchronous Static RAM Center Pwr & Gnd Pinout
The 71124 5V CMOS SRAM
is organized as 128K x 8. The JEDEC
pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL
-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
- JEDEC revolutionary pinout (center power/GND) for reduced noise.
- Equal access and cycle times – Commercial and Industrial: 12/15/20ns
- One Chip Select plus one Output Enable pin
- Bidirectional inputs and outputs directly TTL-compatible
- Low power consumption via chip deselect
- Available in a 32-pin 400 mil Plastic SOJ packages
|Density (Kb)||Bus Width (bits)||Core Voltage (V)||Pkg. Code||Organization||I/O Voltage (V)||Access Time (ns)||I/O Frequency (MHz)||Temp. Range||Architecture||Output Type |
|1024||8||5||PBG32||128K x 8||5.00||12, 15, 20||-40 to 85°C, 0 to 70°C||Asynchronous|| |