Choosing the PLL Bandwidth for Zero Delay Buffers in PCIe Timing Systems
IDT engineer provides a brief tutorial on why zero delay buffers (ZDBs) are offered with two different bandwidths (1 MHz and 3 MHz). The reason has to do with jitter peaking when cascading PLLs.
Presented by Ron Wade, PCI Express timing expert. For more information about IDT’s PCI Express timing solutions, visit www.IDT.com/go/PCIeClocks.